Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 295
PCI Express Non-Transparent Bridge
3.21.1.22 RSDBMSIXV70: Route Secondary Doorbell MSI-X Vector 7 to 0
This register is used to allow flexibility in the SDOORBELL Section 3.21.1.17,
“SDOORBELL: Secondary Doorbell” bits 7 to 0 assignments to one of 4 MSI-X vectors.
Register:RSDBMSIXV70
Bar:PB01BASE
Offset:D0h
Bit Attr Default Description
31:30 RO 0h Reserved
29:28 RW 1h MSI-X Vector assignment for SDOORBELL bit 7
27:26 RO 0h Reserved
25:24 RW 1h MSI-X Vector assignment for SDOORBELL bit 6
23:22 RO 0h Reserved
21:20 RW 1h MSI-X Vector assignment for SDOORBELL bit 5
19:18 RO 0h Reserved
17:16 RW 0h MSI-X Vector assignment for SDOORBELL bit 4
15:14 RO 0h Reserved
13:12 RW 0h MSI-X Vector assignment for SDOORBELL bit 3
11:10 RO 0h Reserved
09:08 RW 0h MSI-X Vector assignment for SDOORBELL bit 2
07:06 RO 0h Reserved
05:04 RW 0h MSI-X Vector assignment for SDOORBELL bit 1
03:02 RO 0h Reserved
01:00 RW 0h
MSI-X Vector assignment for SDOORBELL bit 0
11 = MSI-X vector allocation 3
10 = MSI-X vector allocation 2
01 = MSI-X vector allocation 1
00 = MSI-X vector allocation 0