Datasheet

PCI Express Non-Transparent Bridge

Intel

Xeon

Processor C5500/C3500 Series

Datasheet, Volume 1 February 2010

294 Order Number: 323103-001

3.21.1.21 SPADSEMA4: Scratchpad Semaphore

This register will allow software to share the Scratchpad registers.

Bar:PB01BASE, SB01BASE

Offset:C0h

Bit Attr Default Description

31:01 RO 00h Reserved

R0TS

W1TC

Scratchpad Semaphore

This bit will allow software to synchronize write ownership of the

scratchpad register set. The processor will read the register. If the

returned value is 0, the bit is set by hardware to 1 and the reading

processor is granted ownership of the scratchpad registers. If the returned

value is 1, then the processor on the opposite side of the NTB already

owns the scratchpad registers and the reading processor is not allowed to

modify the scratchpad registers. To relinquish ownership, the owning

processor writes a 1 to this register to reset the value to 0. Ownership of

the scratchpad registers is not set in hardware, i.e. the processor on each

side of the NTB is still capable of writing the registers regardless of the

state of this bit.

Note: For A0 stepping a value of FFFFH must be written to this register

to clear the semaphore. For B0 stepping only bit 0 needs to be

written to 1 in order to clear the semaphore