Datasheet

Intel

Xeon

Processor C5500/C3500 Series

February 2010 Datasheet, Volume 1

Order Number: 323103-001 293

PCI Express Non-Transparent Bridge

3.21.1.20 SPAD[0 - 15]: Scratchpad Registers 0 - 15

This set of 16 registers, SPAD0 through SPAD15, are shared to both sides of the NTB.

They are used to pass information across the bridge.

Bar:PB01BASE, SB01BASE

Offset:70h

Bit Attr Default Description

15:0 RW 00h

Upstream Memory Miss

This register keeps a running count of misses to any of the 3 upstream

memory windows on the secondary side of the NTB. The counter does not

freeze at max count, it rolls over.

Bar:PB01BASE, SB01BASE

Offset:80h, 84h, 88h,8Ch, 90h, 94h, 98h, 9Ch, A0h, A4h, A8h, ACh, B0h, B4h, B8h, BCh

Bit Attr Default Description

31:00 RW 00h

Scratchpad Register n

This set of 16 registers is RW from both sides of the bridge. Synchronization

is provided with a hardware semaphore (SPADSEMA4). Software will use

these registers to pass a protocol, such as a heartbeat, from system to

system across the NTB.