Datasheet
PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
292 Order Number: 323103-001
3.21.1.16 PDBMSK: Primary Doorbell Mask
This register is used to mask the generation of interrupts to the Primary side of the
NTB.
3.21.1.17 SDOORBELL: Secondary Doorbell
This register is valid when in NTB/RP configuration. This register contains the bits used
to generate interrupts to the processor on the Secondary side of the NTB.
3.21.1.18 SDBMSK: Secondary Doorbell Mask
This register is valid when in NTB/RP configuration. This register is used to mask the
generation of interrupts to the Secondary side of the NTB.
3.21.1.19 USMEMMISS: Upstream Memory Miss
This register is used to keep a rolling count of misses to the memory windows on the
upstream port on the secondary side of the NTB. This a rollover counter. This counter
can be used as an aid in determining if there are any programming errors in mapping
the memory windows in the NTB/NTB configuration.
Register:PDBMSK
Bar:PB01BASE, SB01BASE
Offset:62h
Bit Attr Default Description
15:0
Bar: Attr
PB01BASE:
RW
else: RO
FFFFh
Primary Doorbell Mask
This register will allow software to mask the generation of interrupts to the
processor on the Primary side of the NTB.
0 - Allow the interrupt
1 - Mask the interrupt
Register:SDOORBELL
Bar:PB01BASE, SB01BASE
Offset:64h
Bit Attr Default Description
15:0
Bar: Attr
PB01BASE:
RW1S
else: RW1C
00h
Secondary Doorbell Interrupts
These bits are written by the processor on the Primary side of the NTB to
cause an interrupt to be generated to the processor on the Secondary side
of the NTB if the associated mask bit in the SDBMSK register is not set. A 1
is written to this register from the Primary side of the NTB to set the bit, and
to clear the bit a 1 is written from the Secondary side of the NTB.
Note: If both INTx and MSI (NTB PCI CMD bit 10 and NTB MSI Capability
bit 0) interrupt mechanisms are disabled software must poll for
status since no interrupts of either type are generated.
Register:SDBMSK
Bar:PB01BASE, SB01BASE
Offset:66h
Bit Attr Default Description
15:0 RW FFFFh
Secondary Doorbell Mask
This register will allow software to mask the generation of interrupts to the
processor on the Secondary side of the NTB.
0 - Allow the interrupt
1 - Mask the interrupt