Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 291
PCI Express Non-Transparent Bridge
3.21.1.15 PDOORBELL: Primary Doorbell
This register contains the bits used to generate interrupts to the processor on the
Primary side of the NTB.
Register:CBDF
Bar:PB01BASE, SB01BASE
Offset:5Eh
Bit Attr Default Description
15:8 RO 00h
Secondary Bus
Value to be used for the Bus number for ID-based routing.
7:3 RO 00000b
Secondary Device
Value to be used for the Device number for ID-based routing.
2:0 RO 000b
Secondary Function
Value to be used for the Function number for ID-based routing.
Register:PDOORBELL
Bar:PB01BASE, SB01BASE
Offset:60h
Bit Attr Default Description
15
Bar: Attr
PB01BASE:
RW1C
else: RO
0b
Link State Interrupt
This bit is set when a link state change occurs on the Secondary side of the
NTB (Bit 13 of the LNKSTS: PCI Express Link Status Register). This bit is
cleared by writing a 1 from the Primary side of the NTB.
14
Bar: Attr
PB01BASE:
RW1C
else: RW1S
0b
WC_FLUSH_ACK
This bit only has meaning when in NTB/NTB configuration. This bit is set by
hardware when a write cache flush was completed on the remote system.
This bit is cleared by writing a 1 from the Primary side of the NTB.
13:0
Bar: Attr
PB01BASE:
RW1C
else: RW1S
00h
Primary Doorbell Interrupts
These bits are written by the processor on the Secondary side of the NTB to
cause a doorbell interrupt to be generated to the processor on the Primary
side of the NTB if the associated mask bit in the PDBMSK register is not set.
A 1 is written to this register from the Secondary side of the NTB to set the
bit, and to clear the bit a 1 is written from the Primary side of the NTB.
Note: If both INTx and MSI (NTB PCI CMD bit 10 and NTB MSI Capability
bit 0) interrupt mechanisms are disabled software must poll for
status since no interrupts of either type are generated.