Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 29
Features Summary
Single Channel Mode
Independent Channel Mode
Spare Channel Mode
Mirrored Mode
—Lockstep Mode
Dual-channel: Modes; Symmetric (Interleaved); Asymmetric
—Intel
®
Flex Memory Technology
Command launch modes of 1n/2n
Various RAS modes
On-Die Termination (ODT)
•Intel
®
Fast Memory Access (Intel
®
FMA):
Just-in-Time Command Scheduling
Command Overlap
Out-of-Order Scheduling
Asynchronous DRAM Refresh (ADR)
1.4.3 PCI Express
One 16-lane PCI Express port that is fully compliant with the PCI Express Base
Specification, Revision 2.0. The 16 lanes can be bifurcated into two x8 ports, one
x8 port and two x4 ports, or four x4 ports.
Support is provided for one port (X4 or X8) Non-Transparent Bridge (NTB). When
the NTB mode is enabled, the remainder of the x16 lanes can only be configured as
ordinary PCIe root ports.
Negotiating down to narrower widths is supported: A x16 port may negotiate down
to x8, x4, x2, or x1. A x8 port may negotiate down to x4, x2, or x1. A x4 port may
negotiate down to x2, or x1. Restrictions as to how lane reversal is supported exist
when negotiating down to narrower widths. See Table 1.4.3, “PCI Express” on
page 29 for details.
Support for Degraded Mode Operation.
Support for both PCIe Gen1 & Gen2 frequencies.
Automatic discovery, negotiation, and training of link out of reset.
Support peer-to-peer memory reads and memory writes between PCIe links on the
processor, or processors, in DP systems.
Note: Peer-to-peer traffic is not supported between PCIe links on the processor and PCIe links
on the PCH.
64-bit downstream host address format, however since the processor’s
addressiblity is limited to 40 bits (1 TB), bits 63:40 will always be set to zeros.
64-bit upstream host address format, however since the processor’s addressibility
is limited to 40 bits (1 TB) it responds to upstream read transactions with an
Unsupported Request response for addresses above 1 TB. Upstream write
transactions to host addresses beyond 1 TB will be dropped.
PCI Express reference clock is 100-MHz differential clock buffered out of system
clock generator.
Power Management Event (PME) functions.
Static lane numbering reversal: