Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 289
PCI Express Non-Transparent Bridge
03:02
Bar: Attr
PB01BASE:
RW
else: RO
00b
BAR 2/3 Secondary to Primary Snoop Override Control
This bit controls the ability to force all transactions within the Secondary
BAR 2/3 window going from the Secondary side to the Primary side to be
snoop/no-snoop independent of the ATTR field in the TLP header.
00 - All TLP sent as defined by the ATTR field
01 - Force Snoop on all TLPs: ATTR field overridden to set the” No Snoop” bit
= 0 independent of the setting of the ATTR field of the received TLP.
10 - Force No-Snoop on all TLPs: ATTR field overridden to set the “No
Snoop” bit = 1 independent of the setting of the ATTR field of the received
TLP.
11 - Reserved
01
Bar: Attr
PB01BASE:
RW
else: RO
1b
Secondary Link Disable Control
This bit controls the ability to train the link on the secondary side of the NTB.
This bit is used to make sure the primary side is up and operational before
allowing transactions from the secondary side.
0 - Link enabled
1 - Link disabled
Note: This bit logically or’d with the LNKCON bit 4
00
Bar: Attr
PB01BASE:
RW
else: RO
1b
Secondary Configuration Space Lockout Control
This bit controls the ability to modify the Secondary side NTB configuration
registers from the Secondary side link partner.
Note: This does not block MMIO space.
0 - Secondary side can read and write secondary registers
1 - Secondary side modifications locked out but reads are accepted