Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 287
PCI Express Non-Transparent Bridge
3.21.1.11 SBAR4BASE: Secondary BAR 4/5 Base Address
This register is mirrored from the BAR 4/5 register pair in the Configuration Space of
the Secondary side of the NTB. The register is used by the processor on the primary
side of the NTB to examine and load the BAR 4/5 register pair on the Secondary side of
the NTB.
Register:SBAR4BASE
Bar:PB01BASE, SB01BASE
Offset:50h
Bit Attr Default Description
63:nn RWL 00h
Secondary BAR 4/5 Base
This register is reflected into the BAR 4/5 register pair in the Configuration
Space of the Secondary side of the NTB.
Note: These bits will appear to SW as RW.
(nn-
1) :
12
RWL 00h
Reserved
Reserved bits dictated by the size of the memory claimed by the BAR.
Note: These bits will appear to SW as RO.
11:04 RO 00h
Reserved
Granularity must be at least 4 KB.
03 RO 1b
Prefetchable
BAR points to Prefetchable memory.
02:01 RO 10b
Type
Memory type claimed by BAR 4/5 is 64-bit addressable.
00 RO 0b
Memory Space Indicator
BAR resource is memory (as opposed to I/O).