Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
284 Order Number: 323103-001
3.21.1.7 SBAR2XLAT: Secondary BAR 2/3 Translate
This register contains a value used to direct accesses into the memory located on the
Primary side of the NTB made from the Secondary side of the NTB through the window
claimed by BAR 2/3 on the secondary side. The register contains the base address of
the Primary side memory window.
Note: NTB will translate full 64b range. Switch logic will perform address range checks for
both normal and VT-d flows.
Register:SBAR2XLAT
Bar:PB01BASE, SB01BASE
Offset:30h
Bit Attr Default Description
63:nn RWL 00h
Secondary BAR 2/3 Translate
The aligned base address into Primary side memory.
Note: Primary side access will appear as RW to SW. Secondary side access
will appear as RO
(nn-
1) :
12
RWL 00h
Reserved
Reserved bits dictated by the size of the memory claimed by the BAR.
Set by Section 3.20.2.12, “SB23BASE: Secondary BAR 2/3 Base Address
(PCIE NTB Mode)”
Note: Attr will appear as RO to SW
11:00 RO variable
Reserved
Reserved bits dictated by the size of the memory claimed by the BAR.
Set by Section 3.20.2.12, “SB23BASE: Secondary BAR 2/3 Base Address
(PCIE NTB Mode)”
Note: Attr will appear as RO to SW