Datasheet

PCI Express Non-Transparent Bridge

Intel

Xeon

Processor C5500/C3500 Series

Datasheet, Volume 1 February 2010

282 Order Number: 323103-001

3.21.1.5 SBAR2LMT: Secondary BAR 2/3 Limit

This register contains a value used to limit the size of the window exposed by 64-bit

BAR 2/3 to a size less than the power-of-two expressed in the Secondary BAR 2/3 pair.

This register is written by the NTB device driver and will contain the formulated sum of

the base address plus the size of the BAR. This final value equates to the highest

address that will be accepted through this port. Accesses to the memory area above

this register (and below Base + Window Size) will return Unsupported Request.

Note: If the value in SBAR2LMT is set to a value less than the value in Section 3.20.2.12,

“SB23BASE: Secondary BAR 2/3 Base Address (PCIE NTB Mode)” hardware will force

the value in SBAR2LMT to be zero and the full size of the window defined by

Section 3.19.3.21, “SBAR23SZ: Secondary BAR 2/3 Size” will be used.

Note: If the value in SBAR2LMT is set equal to the value in SB23BASE the memory window

for SB23BASE is disabled.

Note: If the value in SBAR2LMT is set to a value greater than the value in the SB23BASE plus

2^SBAR23SZ hardware will force the value in SBAR2LMT to be zero and the full size of

the window defined by SBAR23SZ will be used.

Note: If SBAR2LMT is zero the full size of the window defined by SBAR23SZ will be used.

Bar:PB01BASE, SB01BASE

Offset:20h

Bit Attr Default Description

63:12 RW 00h

Secondary BAR 2/3 Limit

Value representing the size of the memory window exposed by Secondary

BAR 2/3. A value of 00h will disable this register’s functionality, resulting in a

BAR window equal to that described by the BAR

In the case of NTB/NTB SAttr access type is a don’t care

11:00 RO 00h

Reserved

Limit register has a granularity of 4 KB (2

)