Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 279
PCI Express Non-Transparent Bridge
3.21.1.1 PBAR2LMT: Primary BAR 2/3 Limit
This register contains a value used to limit the size of the window exposed by 64-bit
BAR 2/3 to a size less than the power-of-two expressed in the Primary BAR 2/3 pair.
This register is written by the NTB device driver and will contain the formulated sum of
the base address plus the size of the BAR. This final value equates to the highest
address that will be accepted through this port. Accesses to the memory area above
this register (and below Base + Window Size) will return Unsupported Request.
Note: If the value in PBAR2LMT is set to a non-zero value less than the value in
Section 3.19.2.12, “PB23BASE: Primary BAR 2/3 Base Address” hardware will force
the value in PBAR2LMT to be zero and the full size of the window defined by
Section 3.19.3.19, “PBAR23SZ: Primary BAR 2/3 Size” will be used.
Note: If the value in PBAR2LMT is set equal to the value in PB23BASE the memory window for
PB23BASE is disabled.
Note: If the value in PBAR2LMT is set to a value greater than the value in the PB23BASE plus
2^PBAR23SZ hardware will force the value in PBAR2LMT to be zero and the full size of
the window defined by PBAR23SZ will be used.
Note: If PBAR2LMT is zero the full size of the window defined by PBAR23SZ will be used.
Register:PBAR2LMT
Bar:PB01BASE, SB01BASE
Offset:00h
Bit Attr Default Description
63:40 RO 00h
Reserved
Intel
®
Xeon
®
processor C5500/C3500 series limited to 40bit addressing
39:12
Bar: Attr
PB01BASE:
RW
else: RO
00h
Primary BAR 2/3 Limit
Value representing the size of the memory window exposed by Primary BAR
2/3. A value of 00h will disable this register’s functionality, resulting in a BAR
window equal to that described by the BAR
11:00 RO 00h
Reserved
Limit register has a granularity of 4 KB (2
12
)