Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
278 Order Number: 323103-001
Secondary Link State - 1 bit (trained or untrained) (change generates interrupt)
74h F4h
78h F8h
7Ch FCh
Table 93. NTB MMIO Shadow Registers
Table 94. NTB MMIO Map
B2BSPAD0 100h 180h
B2BSPAD1 104h
184h
B2BSPAD2 108h
188h
B2BSPAD3 10Ch
18Ch
B2BSPAD4 110h
190h
B2BSPAD5 114h
194h
B2BSPAD6 118h
198h
B2BSPAD7 11Ch
19Ch
B2BSPAD8 120h
1A0h
B2BSPAD9 124h
1A4h
B2BSPAD10 128h
1A8h
B2BSPAD11 12Ch
1ACh
B2BSPAD12 130h
1B0h
B2BSPAD13 134h
1B4h
B2BSPAD14 138h
1B8h
B2BSPAD15 13Ch
1BCh
B2BDOORBELL 140h 1C0h
B2BBAR0XLAT 144h
1C4h
B2BBAR0XLAT 148h
1C8h
14Ch 1CCh
150h 1D0h
154h 1D4h
158h 1D8h
15Ch 1DCh
160h 1E0h
164h 1E4h
168h 1E8h
16Ch 1ECh
170h 1F0h
174h 1F4h
178h 1F8h
17Ch 1FCh