Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 277
PCI Express Non-Transparent Bridge
3.21 NTB MMIO Space
NTB MMIO space consists of a shared set of MMIO registers (shadowed), primary side
MMIO registers and secondary side MMIO registers.
3.21.1 NTB Shadowed MMIO Space
All shadow registers are visible from the primary side of the NTB. Only some of the
shadow registers are visible from the secondary side of the NTB. See each register
description for visibility.
Table 93. NTB MMIO Shadow Registers
PBAR2LMT
00h SPAD0 80h
04h SPAD1 84h
PBAR4LMT
08h SPAD2 88h
0Ch SPAD3 8Ch
PBAR2XLAT
10h SPAD4 90h
14h SPAD5 94h
PBAR4XLAT
18h SPAD6 98h
1Ch SPAD7 9Ch
SBAR2LMT
20h SPAD8 A0h
24h SPAD9 A4h
SBAR4LMT
28h SPAD10 A8h
2Ch SPAD11 ACh
SBAR2XLAT
30h SPAD12 B0h
34h SPAD13 B4h
SBAR4XLAT
38h SPAD14 B8h
3Ch SPAD15 BCh
SBAR0BASE
40h SPADSEMA4 C0h
44h
C4h
SBAR2BASE
48h
C8h
4Ch
CCh
SBAR4BASE
50h RSDBMSIXV70 D0h
54h RSDBMSIXV158 D4h
NTBCNTL 58h
D8h
CBDF SBDF 5Ch
DCh
PDBMSK PDOORBELL 60h WCCNTRL E0h
SDBMSK SDOORBELL 64h
E4h
68h E8h
6Ch ECh
USMEMMISS 70h F0h