Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
276 Order Number: 323103-001
3.20.3.28 SEXTCAPHDR: Secondary Extended Capability Header
This register identifies the capability structure and points to the next structure. There
are no additional capability structures so this register has been made all zeros.
7:4 RsvdP 0h Reserved.
3RWO 1
No Soft Reset
Indicates IIO does not reset its registers when transitioning from D3hot
to D0.
Note: This bit must be written by BIOS to a ‘1’ so that this register bit
cannot be cleared.
2RsvdP 0hReserved.
1:0 RW 0h
Power State
This 2-bit field is used to determine the current power state of the
function and to set a new power state as well.
00: D0
01: D1 (not supported by IIO)
10: D2 (not supported by IIO)
11: D3_hot
If Software tries to write 01 or 10 to this field, the power state does not
change from the existing power state (which is either D0 or D3hot) and
nor do these bits1:0 change value.
All devices will respond to only Type 0 configuration transactions when in
D3hot state (RP will not forward Type 1 accesses to the downstream link)
and will not respond to memory/IO transactions (i.e. D3hot state is
equivalent to MSE/IOSE bits being clear) as target and will not generate
any memory/IO/configuration transactions as initiator on the primary bus
(messages are still allowed to pass through).
Register:PMCSR
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:E4h
Bit Attr Default Description
Register:SEXTCAPHDR
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:100h
Bit Attr Default Description
31:20 RO 000h
Next Capability Offset
This field points to the next Capability in extended configuration space.
19:16 RO 0h
Capability Version
Set to 1h for this version of the PCI Express logic
15:0 RO 0000h
PCI Express Extended CAP_ID
Assigned for Vendor specific Capability