Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 275
PCI Express Non-Transparent Bridge
3.20.3.27 PMCSR: Power Management Control and Status Register
This register provides status and control information for PM events in the PCI Express
port of the IIO.
19 RO 0b
PME Clock
This field is hardwired to 0h as it does not apply to PCI Express.
18:16 RO 011b
Version
This field is set to 3h (PM 1.2 compliant) as version number for all PCI Express
ports.
15:8 RO 00h
Next Capability Pointer
This is the last capability in the chain and hence set to 0.
7:0 RO 01h
Capability ID
Provides the PM capability ID assigned by PCI-SIG.
Register:PMCAP
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:E0h
Bit Attr Default Description
Register:PMCSR
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:E4h
Bit Attr Default Description
31:24 RO 00h
Data
Not relevant for IIO
23 RO 0h
Bus Power/Clock Control Enable
This field is hardwired to 0h as it does not apply to PCI Express.
22 RO 0h
B2/B3 Support
This field is hardwired to 0h as it does not apply to PCI Express.
21:16 RsvdP 0h Reserved.
15 RO 0h
PME Status
Applies only to RPs
This bit is hard-wired to read-only 0, since this function does not support
PME# generation from any power state.
14:13 RO 0h
Data Scale
Not relevant for IIO
12:9 RO 0h
Data Select
Not relevant for IIO
8 RO 0h
PME Enable
Applies only to RPs.
0: Disable ability to send PME messages when an event occurs
1: Enables ability to send PME messages when an event occurs