Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
274 Order Number: 323103-001
3.20.3.25 SSCNTL: Secondary Side Control
This register provides secondary side control of NTB functions.
.
3.20.3.26 PMCAP: Power Management Capabilities Register
The PM Capabilities Register defines the capability ID, next pointer and other power
management related support. The following PM registers /capabilities are added for
software compliance.
Register:SSCNTL
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:D4h
Bit Attr Default Description
15:01 RO 0h Reserved
00 RW 0b
NTB Secondary side - MSI-X Single Message Vector: This bit when set, causes
only a single MSI-X message to be generated if MSI-X is enabled. This bit
affects the default value of the MSI-X Table Size field in the Section 3.20.3.11,
“MSIXMSGCTRL: MSI-X Message Control Register”
Register:PMCAP
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:E0h
Bit Attr Default Description
31:27 RO 00000b
PME Support
Indicates the PM states within which the function is capable of sending a PME
message.
NTB secondary side does not forward PME messages.
Bit 31 = D3cold
Bit 30 = D3hot
Bit 29 = D2
Bit 28 = D1
Bit 27 = D0
26 RO 0b
D2 Support
IIO does not support power management state D2.
25 RO 0b
D1 Support
IIO does not support power management state D1.
24:22 RO 000b
AUX Current
Device does not support auxiliary current
21 RO 0b
Device Specific Initialization
Device initialization is not required
20 RV 0b Reserved.