Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 273
PCI Express Non-Transparent Bridge
Register:DEVCTRL2
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:B8h
Bit Attr Default Description
15:5 RO 0h Reserved
4RW 0
Completion Timeout Disable – When set to 1b, this bit disables the
Completion Timeout mechanism for all NP tx that IIO issues on the PCIE/DMI
link and in the case of Intel
®
QuickData Technology DMA, for all NP tx that
DMA issues upstream. When 0b, completion timeout is enabled.
Software can change this field while there is active traffic in the root port.
3:0 RW 0000b
Completion Timeout Value on NP Tx that IIO issues on PCIE/DMI – In
Devices that support Completion Timeout programmability, this field allows
system software to modify the Completion Timeout range. The following
encodings and corresponding timeout ranges are defined:
0000b = 10ms to 50ms
0001b = Reserved (IIO aliases to 0000b)
0010b = Reserved (IIO aliases to 0000b)
0101b = 16ms to 55ms
0110b = 65ms to 210ms
1001b = 260ms to 900ms
1010b = 1s to 3.5s
1101b = 4s to 13s
1110b = 17s to 64s
When OS selects 17s to 64s range, Section , “BDF 030 Offset 232H. This
register exist in both RP and NTB modes. It is documented in RP
Section 3.4.5.34, “XPGLBERRPTR - XP Global Error Pointer Register”. See
Volume 2 of the Datasheet.” on page 237 further controls the timeout value
within that range. For all other ranges selected by OS, the timeout value
within that range is fixed in IIO hardware.
Software can change this field while there is active traffic in the root port.
This value will also be used to control PME_TO_ACK Timeout. That is this
field sets the timeout value for receiving a PME_TO_ACK message after a
PME_TURN_OFF message has been transmitted. The PME_TO_ACK Timeout
has meaning only if bit 6 of MISCCTRLSTS register is set to a 1b.