Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
272 Order Number: 323103-001
3.20.3.23 DEVCAP2: PCI Express Device Capabilities Register 2
3.20.3.24 DEVCTRL2: PCI Express Device Control Register 2
This register is intended to be controlled from the primary side of the NTB at the mirror
location of BDF 030, Offset 1B8h. This register provides visibility from the secondary
side of the NTB.
Register:DEVCAP2
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:B4h
Bit Attr Default Description
31:6 RO 0h Reserved
5RO 0
Alternative RID Interpretation (ARI) Capable - This bit is set to 1b indicating
Root Port supports this capability.
NOTE: This bit is reserved and not applicable for Endpoints
4RO 1
Completion Timeout Disable Supported - IIO supports disabling
completion timeout
3:0 RO 1110b
Completion Timeout Values Supported – This field indicates device support for
the optional Completion Timeout programmability mechanism. This
mechanism allows system software to modify the Completion Timeout range.
Bits are one-hot encoded and set according to the table below to show timeout
value ranges supported. A device that supports the optional capability of
Completion Timeout Programmability must set at least two bits.
Four time values ranges are defined:
Range A: 50us to 10ms
Range B: 10ms to 250ms
Range C: 250ms to 4s
Range D: 4s to 64s
Bits ares set according to table below to show timeout value ranges supported.
0000b: Completions Timeout programming not supported -- values is fixed by
implementation in the range 50us to 50ms.
0001b: Range A
0010b: Range B
0011b: Range A & B
0110b: Range B & C
0111b: Range A, B, & C
1110b: Range B, C & D
1111b: Range A, B, C & D
All other values are reserved.
IIO supports timeout values up to 10ms-64s.