Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 271
PCI Express Non-Transparent Bridge
11 RO 0
Link Training
This field indicates the status of an ongoing link training session in the PCI
Express port
0: LTSSM has exited the recovery/configuration state
1: LTSSM is in recovery/configuration state or the Retrain Link was set but
training has not yet begun.
The IIO hardware clears this bit once LTSSM has exited the recovery/
configuration state. See the PCI Express Base Specification, Revision 2.0 for
details of which states within the LTSSM would set this bit and which states
would clear this bit.
10 RO 0 Reserved
9:4 RO 0h
Negotiated Link Width
This field indicates the negotiated width of the given PCI Express link after
training is completed. Only x1, x2, x4, x8 and x16 link width negotiations are
possible in IIO. A value of 0x01 in this field corresponds to a link width of x1,
0x02 indicates a link width of x2 and so on, with a value of 0x16 for a link
width of x16.
The value in this field is reserved and could show any value when the link is
not up. Software determines if the link is up or not by reading bit 13 of this
register.
3:0 RO 1h
Current Link Speed
This field indicates the negotiated Link speed of the given PCI Express Link.
0001- 2.5 Gbps
0010 - 5Gbps (IIO will never set this value when Gen2_OFF fuse is blown)
Others - Reserved
The value in this field is not defined and could show any value, when the link is
not up. Software determines if the link is up or not by reading bit 13 of this
register.
Register:LNKSTS
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:A2h
Bit Attr Default Description