Datasheet
PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
270 Order Number: 323103-001
3.20.3.22 LNKSTS: PCI Express Link Status Register
Note: This register is a secondary view into the LNKSTS register. BIOS must set some
registers prior to use. See Section 3.19.4.25, “LNKSTS: PCI Express Link Status
Register” .
The PCI Express Link Status register provides information on the status of the PCI
Express Link such as negotiated width, training etc.
Register:LNKSTS
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:A2h
Bit Attr Default Description
15
Rsvd
P
0
Link Autonomous Bandwidth Status
This bit is not applicable and is reserved for Endpoints
14
Rsvd
P
0
Link Bandwidth Management Status
This bit is not applicable and is reserved for Endpoints
13 RO 0
Data Link Layer Link Active
Set to 1b when the Data Link Control and Management State Machine is in the
DL_Active state, 0b otherwise.
On a downstream port or upstream port, when this bit is 0b, the transaction
layer associated with the link will abort all transactions that would otherwise
be routed to that link.
12 RO 1
Slot Clock Configuration
This bit indicates whether IIO receives clock from the same xtal that also
provides clock to the device on the other end of the link.
1: indicates that same xtal provides clocks to devices on both ends of the link
0: indicates that different xtals provide clocks to devices on both ends of the
link