Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
268 Order Number: 323103-001
3.20.3.21 LNKCON: PCI Express Link Control Register
The PCI Express Link Control register controls the PCI Express Link specific parameters
Note: This register is a secondary view into the LNKCAP register. Some additional
controllability is available through the primary side equivalent register. See
Section 3.19.4.24, “LNKCON: PCI Express Link Control Register”
Note: In NTB/RP mode RP will program this register. In NTB/NTB mode local host BIOS will
program this register.
Register:LNKCON
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:A0h
Bit Attr Default Description
15:12 RsvdP 0h Reserved
11 RsvdP 0b
Link Autonomous Bandwidth Interrupt Enable -
This bit is not applicable and is reserved for Endpoints
10 RsvdP 0b
Link Bandwidth Management Interrupt Enable -
This bit is not applicable and is reserved for Endpoints
09 RO 0b
Hardware Autonomous Width Disable: IIO never changes a configured
link width for reasons other than reliability.
08 RO 0b Enable Clock Power Management: N/A to IIO
07 RW 0b
Extended Synch
This bit when set forces the transmission of additional ordered sets when
exiting L0s and when in recovery. See PCI Express Base Specification,
Revision 2.0 for details.
06 RW 0b
Common Clock Configuration
IIO does nothing with this bit
05 RsvdP 0b
Retrain Link
This bit is not applicable and is reserved for Endpoints