Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 267
PCI Express Non-Transparent Bridge
14:12 RO 011
L0s Exit Latency
This field indicates the L0s exit latency (i.e L0s to L0) for the PCI-Express
port.
000: Less than 64 ns
001: 64 ns to less than 128 ns
010: 128 ns to less than 256 ns
011: 256 ns to less than 512 ns
100: 512 ns to less than 1 is
101: 1 is to less than 2 is
110: 2 is to 4 is
111: More than 4 is
11:10 RO 11
Active State Link PM Support
This field indicates the level of active state power management supported
on the given PCI-Express port.
00: Disabled
01: L0s Entry Supported
10: Reserved
11: L0s and L1 Supported
9:4 RO 001000b
Maximum Link Width
This field indicates the maximum width of the given PCI Express Link
attached to the port.
000001: x1
000010: x2
1
000100: x4
001000: x8
010000: x16
Others - Reserved
3:0 RO 0010b
Link Speeds Supported
IIO supports both 2.5Gbps and 5Gbps speeds if Gen2_OFF fuse is OFF else
it supports only Gen1
0001b = 2.5 GT/s Link speed supported
0010b = 5.0 GT/s and 2.5 GT/s link speed supported
This field defaults to 0010b if Gen2_OFF fuse is OFF
This field defaults to 0001b if Gen2_OFF fuse is ON
1. There are restrictions with routing x2 lanes from IIO to a slot. See Section 3.3, “PCI Express Link
Characteristics - Link Training, Bifurcation, Downgrading and Lane Reversal Support” (IOH Platform
Architecture Specification) for details.
Register:LNKCAP
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:9Ch
Bit Attr Default Description