Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
264 Order Number: 323103-001
4 RO 0
Enable Relaxed Ordering
Not applicable since the NTB is never the originator of a TLP.
This bit has no impact on forwarding of relaxed ordering attribute on peer
requests.
3RO 0
Unsupported Request Reporting Enable
Applies only to the PCI Express/DMI ports. This bit controls the reporting of
unsupported requests that IIO itself detects on requests its receives from a
PCI Express/DMI port.
0: Reporting of unsupported requests is disabled
1: Reporting of unsupported requests is enabled.
Note: This register provides no functionality on the secondary side of the
NTB. The NTB never reports errors outbound. All errors are sent
towards local host that are detected on the link.
2RO 0
Fatal Error Reporting Enable
Applies only to the PCI Express RP/PCI Express NTB Secondary interface/DMI
ports. Controls the reporting of fatal errors that IIO detects on the PCI
Express/DMI interface.
0: Reporting of Fatal error detected by device is disabled
1: Reporting of Fatal error detected by device is enabled
Note: This register provides no functionality on the secondary side of the
NTB. The NTB never reports errors outbound. All errors are sent
towards local host that are detected on the link.
1RO 0
Non Fatal Error Reporting Enable
Applies only to the PCI Express RP/PCI Express NTB Secondary interface/DMI
ports. Controls the reporting of non-fatal errors that IIO detects on the PCI
Express/DMI interface.
0: Reporting of Non Fatal error detected by device is disabled
1: Reporting of Non Fatal error detected by device is enabled
Note: This register provides no functionality on the secondary side of the
NTB. The NTB never reports errors outbound. All errors are sent
towards local host that are detected on the link.
0RO 0
Correctable Error Reporting Enable
Applies only to the PCI Express RP/PCI Express NTB Secondary interface/DMI
ports. Controls the reporting of correctable errors that IIO detects on the PCI
Express/DMI interface
0: Reporting of link Correctable error detected by the port is disabled
1: Reporting of link Correctable error detected by port is enabled
Note: This register provides no functionality on the secondary side of the
NTB. The NTB never reports errors outbound. All errors are sent
towards local host that are detected on the link.
Register:DEVCTRL
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:98h
PCIE_ONLY
Bit Attr Default Description