Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
260 Order Number: 323103-001
3.20.3.15 PXPNXTPTR: PCI Express Next Pointer Register
The PCI Express Capability List register enumerates the PCI Express Capability
structure in the PCI 3.0 configuration space.
3.20.3.16 PXPCAP: PCI Express Capabilities Register
The PCI Express Capabilities register identifies the PCI Express device type and
associated capabilities.
Register:PXPNXTPTR
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:91h
Bit Attr Default Description
7:0 RWO E0h
Next Ptr
This field is set to the PCI PM capability.
Register:PXPCAP
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:92h
Bit Attr Default Description
15:14
Rsvd
P
00b Reserved
13:9 RO 00000b
Interrupt Message Number
Applies only to the RPs.
This field indicates the interrupt message number that is generated for PM/HP
events. When there are more than one MSI interrupt Number, this register
field is required to contain the offset between the base Message Data and the
MSI Message that is generated when the status bits in the slot status register
or RP status registers are set. IIO assigns the first vector for PM/HP events
and so this field is set to 0.
8RWO 0b
Slot Implemented
Applies only to the RPs for NTB this value is kept at 0b.
1: indicates that the PCI Express link associated with the port is connected to
a slot.
0: indicates no slot is connected to this port.
This register bit is of type “write once” and is controlled by BIOS/special
initialization firmware.
7:4 RO 0000b
Device/Port Type
This field identifies the type of device.
0000b = PCI Express Endpoint.
3:0 RWO 2h
Capability Version
This field identifies the version of the PCI Express capability structure. Set to
2h for PCI Express devices for compliance with the extended base registers.