Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 259
PCI Express Non-Transparent Bridge
3.20.3.13 PBAOFF_BIR: MSI-X Pending Bit Array Offset and BAR Indicator
Register default: 00005000h
3.20.3.14 PXPCAPID: PCI Express Capability Identity Register
The PCI Express Capability List register enumerates the PCI Express Capability
structure in the PCI 3.0 configuration space.
Register:PBAOFF_BIR
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:88h
Bit Attr Default Description
31:03 RO 00000A00h
Table Offset
MSI-X PBA Structure is at offset 20K from the SB01BASE BAR address. See
Section 3.21.3.4, “SMSIXPBA: Secondary MSI-X Pending Bit Array Register”
for details.
Note: Offset placed at 20K so that it can also be visible through the primary
BAR for debug purposes.
02:00 RO 0h
PBA BIR
Indicates which one of a function’s Base Address registers, located beginning
at 10h in Configuration Space, is used to map the function’s MSI-X Table into
Memory Space.
BIR Value Base Address register
0 10h
1 14h
2 18h
3 1Ch
4 20h
5 24h
6 Reserved
7 Reserved
For a 64-bit Base Address register, the Table BIR indicates the lower DWORD.
Register:PXPCAPID
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:90h
Bit Attr Default Description
7:0 RO 10h
Capability ID
Provides the PCI Express capability ID assigned by PCI-SIG.
Required by PCI Express Base Specification, Revision 2.0 to be this value.