Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
258 Order Number: 323103-001
3.20.3.12 TABLEOFF_BIR: MSI-X Table Offset and BAR Indicator Register (BIR)
Register default: 00004000h
10:00 RO 003h
Table Size
System software reads this field to determine the MSI-X Table Size N, which is
encoded as N-1. For example, a returned value of “00000000011” indicates a
table size of 4.
NTB table size is 4, encoded as a value of 003h
The value in this field depends on the setting of Section 3.20.3.23, “DEVCAP2:
PCI Express Device Capabilities Register 2” bit 0.
When SSCNTL, bit 0 = ‘0’ (default) Table size is 4, encoded as a value of 003h
When SSCNTL, bit 0 =‘1’ Table size is 1, encoded as a value of 000h
Register:
MSIXMSGCTRL
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:82h
Bit Attr Default Description
Register:TABLEOFF_BIR
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:84h
Bit Attr Default Description
31:03 RO 00000800h
Table Offset
MSI-X Table Structure is at offset 16K from the SB01BASE BAR address. See
Section 3.21.2.1, “PMSIXTBL[0-3]: Primary MSI-X Table Address Register 0 -
3” for the start of details relating to MSI-X registers.
Note: Offset placed at 16K so that it can also be visible through the primary
BAR for debug purposes.
02:00 RO 0h
Table BIR
Indicates which one of a function’s Base Address registers, located beginning
at 10h in Configuration Space, is used to map the function’s MSI-X Table into
Memory Space.
BIR Value Base Address register
0 10h
1 14h
2 18h
3 1Ch
4 20h
5 24h
6 Reserved
7 Reserved
For a 64-bit Base Address register, the Table BIR indicates the lower DWORD.