Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 257
PCI Express Non-Transparent Bridge
3.20.3.9 MSIXCAPID: MSI-X Capability ID
3.20.3.10 MSIXNXTPTR: MSI-X Next Pointer
3.20.3.11 MSIXMSGCTRL: MSI-X Message Control Register
Register:MSIXCAPID
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:80h
Bit Attr Default Description
7:0 RO 11h
Capability ID
Assigned by PCI-SIG for MSI-X.
Register:
MSIXNXTPTR
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:81h
Bit Attr Default Description
7:0 RO 90h
Next Ptr
This field is set to 90h for the next capability list (PCI Express capability
structure) in the chain.
Register:
MSIXMSGCTRL
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:82h
Bit Attr Default Description
15 RW 0b
MSI-X Enable
Software uses this bit to enable MSI-X method for signaling
0: NTB is prohibited from using MSI-X to request service
1: MSI-X method is chosen for NTB interrupts
Note: Software must disable INTx and MSI for this device when using MSI-X
14 RW 0b
Function Mask
If = 1b, all the vectors associated with the NTB are masked, regardless of the
per vector mask bit state.
If = 0b, each vector’s mask bit determines whether the vector is masked or
not. Setting or clearing the MSI-X function mask bit has no effect on the state
of the per-vector Mask bit.
13:11 RO 0h Reserved.