Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
256 Order Number: 323103-001
3.20.3.7 MSIMSK: MSI Mask Bit Register
The Mask Bit register enables software to disable message sending on a per-vector
basis.
3.20.3.8 MSIPENDING: MSI Pending Bit Register
The Mask Pending register enables software to defer message sending on a per-vector
basis.
Table 92. MSI Vector Handling and Processing by IIO on Secondary Side
Number of Messages enabled by Software Events IV[7:0]
1PD[15:00]
xxxxxxxx
1
1. The term “xxxxxx” in the Interrupt vector denotes that software initializes them and IIO will not modify any
of the “x” bits except the LSB as indicated in the table as a function of MMEN
Register:MSIMSK
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:70h
Bit Attr Default Description
31:01
Rsvd
P
0h Reserved
00 RW 0h
Mask Bit
For each Mask bit that is set, the PCI Express port is prohibited from sending
the associated message.
NTB supports up to 1 messages
Corresponding bits are masked if set to ‘1’
Register:MSIPENDING
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:74h
Bit Attr Default Description
31:01
Rsvd
P
0h Reserved
00 RO 0h
Pending Bits
For each Pending bit that is set, the PCI Express port has a pending associated
message.
NTB supports 1 message
Corresponding bits are pending if set to ‘1’