Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 255
PCI Express Non-Transparent Bridge
3.20.3.6 MSIDR: MSI Data Register
The MSI Data Register contains all the data (interrupt vector) related to MSI interrupts
from the root ports.
Register:MSIUAR
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:68h
Bit Attr Default Description
31:00 RW 00000000h
Upper Address MSB
If the MSI Enable bit (bit 0 of the MSICTRL) is set, the contents of this register
(if non-zero) specify the upper 32-bits of a 64-bit message address
(AD[63::32]). If the contents of this register are zero, the function uses the
32 bit address specified by the message address register.
Register:MSIDR
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:6Ch
Bit Attr Default Description
31:16 RO 0000h Reserved.
15 RW 0h
Trigger Mode
0 - Edge Triggered
1 - Level Triggered
IIO does nothing with this bit other than passing it along to the Intel
®
QPI
14 RW 0h
Level
0 - Deassert
1 - Assert
IIO does nothing with this bit other than passing it along to the Intel
®
QPI
13:12 RW 0h Don’t care for IIO
11:8 RW 0h
Delivery Mode
0000 – Fixed: Trigger Mode can be edge or level.
0001 – Lowest Priority: Trigger Mode can be edge or level.
0010 – SMI/PMI/MCA - Not supported via MSI of root port
0011 – Reserved - Not supported via MSI of root port
0100 – NMI - Not supported via MSI of root port
0101 – INIT - Not supported via MSI of root port
0110 – Reserved
0111 – ExtINT - Not supported via MSI of root port
1000-1111 - Reserved
7:0 RW 0h
Interrupt Vector
The interrupt vector (LSB) will be modified by the IIO to provide context
sensitive interrupt information for different events that require attention from
the processor.
Depending on the number of Messages enabled by the processor, Table 91
illustrates how the IIO distributes these vectors