Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
254 Order Number: 323103-001
3.20.3.4 MSIAR: MSI Lower Address Register
The MSI Lower Address Register (MSIAR) contains the lower 32b system specific
address information to route MSI interrupts.
3.20.3.5 MSIUAR: MSI Upper Address Register
The optional MSI Upper Address Register (MSIAR) contains the upper 32b system
specific address information to route MSI interrupts.
0RW 0b
MSI Enable
The software sets this bit to select platform-specific interrupts or transmit MSI
messages.
0: Disables MSI from being generated.
1: Enables the PCI Express port to use MSI messages for RAS, provided bit 4
in Section 3.19.4.20, “MISCCTRLSTS: Misc. Control and Status Register” on
page 216 is clear and also enables the Express port to use MSI messages for
PM and HP events at the root port provided these individual events are not
enabled for ACPI handling (see Section 3.19.4.20, “MISCCTRLSTS: Misc.
Control and Status Register” on page 216) for details.
Note: Software must disable INTx and MSI-X for this device when using MSI
Register:
MSICTRL
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:62h
Bit Attr Default Description
Register:MSIAR
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:64h
Bit Attr Default Description
31:20 RW 0h
Address MSB
This field specifies the 12 most significant bits of the 32-bit MSI address. This
field is R/W.
19:12 RW 00h
Address Destination ID
This field is initialized by software for routing the interrupts to the appropriate
destination.
11:4 RW 00h
Address Extended Destination ID
This field is not used by IA32 processor
3RW 0h
Address Redirection Hint
0: directed
1: redirectable
2RW 0h
Address Destination Mode
0: physical
1: logical
1:0 RO 0h Reserved.