Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 253
PCI Express Non-Transparent Bridge
3.20.3.3 MSICTRL: MSI Control Register
Register:MSICTRL
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:62h
Bit Attr Default Description
15:9 RV 00h Reserved.
8RO 1b
Per-vector masking capable
This bit indicates that PCI Express ports support MSI per-vector masking.
7RO 1b
64-bit Address Capable
A PCI Express Endpoint must support the 64-bit Message Address version of
the MSI Capability structure
1: Function is capable of sending 64-bit message address
0: Function is not capable of sending 64-bit message address.
Notes:
•
For B0 stepping this field is RO = 1
• For A0 stepping this field is RO = 0 so can only be connected to CPU
requiring 32b MSI address.
6:4 RW 000b
Multiple Message Enable
Applicable only to PCI Express ports. Software writes to this field to indicate
the number of allocated messages which is aligned to a power of two. When
MSI is enabled, the software will allocate at least one message to the device.
A value of 000 indicates 1 message. See Table 91 for a discussion on how the
interrupts are distributed amongst the various sources of interrupt based on
the number of messages allocated by software for the PCI Express NTB port.
Value
Number of Messages Requested
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = Reserved
111b = Reserved
3:1 RO 000b
Multiple Message Capable
IIO’s PCI Express NTB port supports one message for all internal events.
Value Number of Messages Requested
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = Reserved
111b = Reserved