Datasheet
PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
252 Order Number: 323103-001
3.20.2.19 MINGNT: Minimum Grant Register
.
3.20.2.20 MAXLAT: Maximum Latency Register
.
3.20.3 Device-Specific PCI Configuration Space - 0x40 to 0xFF
3.20.3.1 MSICAPID: MSI Capability ID
3.20.3.2 MSINXTPTR: MSI Next Pointer
Register:INTPIN
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:3Eh
Bit Attr Default Description
7:0 RO 00h
Minimum Grant: This register does not apply to PCI Express. It is hard-coded
to “00”h.
Register:MAXLAT
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:3Fh
Bit Attr Default Description
7:0 RO 00h
Maximum Latency: This register does not apply to PCI Express. It is hard-
coded to “00”h.
Register:
MSICAPID
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:60h
Bit Attr Default Description
7:0 RO 05h
Capability ID
Assigned by PCI-SIG for MSI.
Register:
MSINXTPTR
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function:0
Offset:61h
Bit Attr Default Description
7:0 RWO 80h
Next Ptr
This field is set to 80h for the next capability list (PCI Express capability
structure) in the chain.