Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 251
PCI Express Non-Transparent Bridge
3.20.2.17 INTL: Interrupt Line Register
The Interrupt Line register is used to communicate interrupt line routing information
between initialization code and the device driver. This register is not used in newer
OSes and is just kept as RW for compatibility purposes only.
3.20.2.18 INTPIN: Interrupt Pin Register
The INTP register identifies legacy interrupts for INTA, INTB, INTC and INTD as
determined by BIOS/firmware. These are emulated over the DMI port using the
appropriate Assert_Intx commands.
Register:INTL
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:3Ch
Bit Attr Default Description
7:0 RW 00h
Interrupt Line
This bit is RW for devices that can generate a legacy INTx message and is
needed only for compatibility purposes.
Register:INTPIN
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:3Dh
Bit Attr Default Description
7:0 RWO 01h
INTP: Interrupt Pin
This field defines the type of interrupt to generate for the PCI-Express port.
001: Generate INTA
010: Generate INTB
011: Generate INTC
100: Generate INTD
Others: Reserved
BIOS/configuration software has the ability to program this register once
during boot to set up the correct interrupt for the port.
Note: While the PCI spec. defines only one interrupt line (INTA#) for a
single function device, the logic for the NTB has been modified to
meet customer requests for programmability of the interrupt pin.
BIOS should always set this to INTA# for standard OS’s.