Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
250 Order Number: 323103-001
3.20.2.14 SUBVID: Subsystem Vendor ID (Dev#3, PCIE NTB Sec Mode)
This register identifies the vendor of the subsystem.
3.20.2.15 SID: Subsystem Identity (Dev#3, PCIE NTB Sec Mode)
This register identifies a particular subsystem.
3.20.2.16 CAPPTR: Capability Pointer
The CAPPTR is used to point to a linked list of additional capabilities implemented by
the device. It provides the offset to the first set of capabilities registers located in the
PCI compatible space from 40h.
Register:SUBVID
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:2Ch
Bit Attr Default Description
15:0 RWO 0000h
Subsystem Vendor ID: This field must be programmed during boot-up to
indicate the vendor of the system board. When any byte or combination of
bytes of this register is written, the register value locks and cannot be further
updated.
Register:SID
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:2Eh
Bit Attr Default Description
15:0 RWO 0000h
Subsystem ID: This field must be programmed during BIOS initialization.
When any byte or combination of bytes of this register is written, the register
value locks and cannot be further updated.
Register:CAPPTR
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:34h
Bit Attr Default Description
7:0 RWO 60h
Capability Pointer
Points to the first capability structure for the device.