Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 249
PCI Express Non-Transparent Bridge
3.20.2.13 SB45BASE: Secondary BAR 4/5 Base Address
This register is BAR 4/5 for the secondary side of the NTB. This configuration register
can be modified via configuration transaction from the secondary side of the NTB and
can also be modified from the primary side of the NTB via MMIO transaction to
Section 3.21.1.11, “SBAR4BASE: Secondary BAR 4/5 Base Address”
Note: SW must program upper DW first and then lower DW. If lower DW is programmed first
HW will clear the lower DW.
Register default: 000000800000000CH
Register:SB45BASE
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:20h
Bit Attr Default Description
63:nn RWL variable
Secondary BAR 4/5 Base
Sets the location of the BAR written by SW
Notes:
• The “nn” indicates the least significant bit that is writable. The number
of bits that are writable in this register is dictated by the value loaded
into the SBAR45SZ register by the BIOS at initialization time (before
BIOS PCI enumeration).
• For the special case where SBAR45SZ = ‘0’, bits 63:00 are all RO=’0’
resulting in the BAR being disabled.
• Default is set to 512 GB
(nn-
1) :
12
RO variable
Reserved
Reserved bits dictated by the size of the memory claimed by the BAR.
Set by Section 3.19.3.22, “SBAR45SZ: Secondary BAR 4/5 Size”
Granularity must be at least 4 KB.
Note: For the special case where SBAR45SZ = ‘0’, bits 63:00 are all
RO=’0’ resulting in the BAR being disabled.
11:04 RO 00h
Reserved
Granularity must be at least 4 KB.
03 RO 1b
Prefetchable
BAR points to Prefetchable memory.
02:01 RO 10b
Type
Memory type claimed by BAR 4/5 is 64-bit addressable.
00 RO 0b
Memory Space Indicator
BAR resource is memory (as opposed to I/O).