Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 247
PCI Express Non-Transparent Bridge
3.20.2.10 BIST: Built-In Self Test
This register is used for reporting control and status information of BIST checks within
a PCI Express port. It is not supported in Intel
®
Xeon
®
processor C5500/C3500 series.
3.20.2.11 SB01BASE: Secondary BAR 0/1 Base Address (PCIE NTB Mode)
This register is BAR 0/1 for the secondary side of the NTB. This configuration register
can be modified via configuration transaction from the secondary side of the NTB and
can also be modified from the primary side of the NTB via MMIO transaction to
Section 3.21.1.9, “SBAR0BASE: Secondary BAR 0/1 Base Address” .
Note: SW must program upper DW first and then lower DW. If lower DW is programmed first
HW will clear the lower DW.
Register:BIST
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:0Fh
Bit Attr Default Description
7:0 RO 0h
BIST_TST: BIST Tests
Not supported. Hardwired to 00h
Register:SB01BASE
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:10h
Bit Attr Default Description
63:15 RW 00h
Secondary BAR 0/1 Base
This register is reflected into the BAR 0/1 register pair in the
Configuration Space of the Secondary side of the NTB written by SW
on a 32KB alignment.
14:04 RO 00h
Reserved
Fixed size of 32KB.
3RWO 1b
Prefetchable
1 = BAR points to Prefetchable memory (default)
0 = BAR points to Non-Prefetchable memory
2:1 RO 10b
Type
Memory type claimed by BAR 2/3 is 64-bit addressable.
0RO 0b
Memory Space Indicator
BAR resource is memory (as opposed to I/O).