Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
246 Order Number: 323103-001
3.20.2.7 CLSR: Cacheline Size Register
3.20.2.8 PLAT: Primary Latency Timer
This register denotes the maximum time slice for a burst transaction in legacy PCI 2.3
on the primary interface. It does not affect/influence PCI Express functionality.
3.20.2.9 HDR: Header Type Register (Dev#3, PCIe NTB Sec Mode)
This register identifies the header layout of the configuration space.
Register:CLSR
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:0Ch
Bit Attr Default Description
7:0 RW 0h
Cacheline Size
This register is set as RW for compatibility reasons only. Cacheline size for IIO
is always 64B. IIO hardware ignore this setting.
Register:PLAT
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:0Dh
Bit Attr Default Description
7:0 RO 0h
Prim_Lat_timer: Primary Latency Timer
Not applicable to PCI-Express. Hardwired to 00h.
Register:HDR
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:0Eh
PCIE_ONLY
Bit Attr Default Description
7RO 0
Multi-function Device
This bit defaults to 0 for PCI Express NTB port.
6:0 RO 00h
Configuration Layout
This field identifies the format of the configuration header layout. It is Type0 for PCI
Express NTB port.
The
default is 00h, indicating a “non-bridge function”.