Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 245
PCI Express Non-Transparent Bridge
3.20.2.5 RID: Revision Identification Register
This register contains the revision number of the IIO. The revision number steps the
same across all devices and functions i.e. individual devices do not step their RID
independently.
IIO supports the CRID feature where in this register’s value can be changed by BIOS.
See Section 3.2.2, “Compatibility Revision ID” in Volume 2 of the Datasheet for details.
3.20.2.6 CCR: Class Code Register
This register contains the Class Code for the device.
Register:RID
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:08h
Bit Attr Default Description
7:4 RO 0
Major Revision
Steppings which require all masks to be regenerated.
0: A stepping
1: B stepping
3:0 RO 0
Minor Revision
Incremented for each stepping which does not modify all masks. Reset for each
major revision.
0: x0 stepping
1: x1 stepping
2: x2 stepping
Register:CCR
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:09h
Bit Attr Default Description
23:16 RO 06h
Base Class
For PCI Express NTB port this field is hardwired to 06h, indicating it is a “Bridge
Device”.
15:8 RO 80h
Sub-Class
For PCI Express NTB port, this field hardwired to 80h to indicate a “Other bridge
type”.
7:0 RO 00h
Register-Level Programming Interface
This field is hardwired to 00h for PCI Express NTB port.