Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
244 Order Number: 323103-001
11 RW1C 0
Signaled Target Abort
This bit is set when the NTB port forwards a completer abort (CA)
completion status from the primary interface to the secondary interface.
10:9 RO 0h
DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0.
8RW1C 0
Master Data Parity Error
This bit is set if the Parity Error Response bit in the PCI Command register is
set and the
• Requestor receives a poisoned completion on the secondary interface
or
• Requestor forwards a poisoned write request (including MSI/MSI-X
writes) from the primary interface to the secondary interface.
7RO 0
Fast Back-to-Back
Not applicable to PCI Express. Hardwired to 0.
6RO 0Reserved
5RO 0
66MHz capable
Not applicable to PCI Express. Hardwired to 0.
4RO 1
Capabilities List
This bit indicates the presence of a capabilities list structure
3RO 0
INTx Status
When Set, indicates that an INTx emulation interrupt is pending internally in
the Function.
2:0 RV 0h Reserved
Register:PCISTS
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:06h
Bit Attr Default Description