Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
242 Order Number: 323103-001
3RO 0
Special Cycle Enable
Not applicable to PCI Express must be hardwired to 0.
2RW 0
Bus Master Enable
1: When this bit is Set, the PCIE NTB will forward Memory Requests that it
receives on its primary internal interface to its secondary external link
interface.
0: When this bit is Clear, the PCIE NTB will not forward Memory Requests
that it receives on its primary internal interface. Memory requests received
on the primary internal interface will be returned to requester as an
Unsupported Requests UR.
Requests other than Memory Requests are not controlled by this bit.
Default value of this bit is 0b.
1RW 0
Memory Space Enable
1: Enables a PCI Express port’s memory range registers to be decoded as
valid target addresses for transactions from secondary side.
0: Disables a PCI Express port’s memory range registers (including the
Configuration Registers range registers) to be decoded as valid target
addresses for transactions from secondary side.
0RO 0
IO Space Enable
Controls a device's response to I/O Space accesses. A value of 0 disables
the device response. A value of 1 allows the device to respond to I/O
Space accesses. State after RST# is 0.
NTB does not support I/O space accesses.
Hardwired to 0
Register:PCICMD
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:04h
Bit Attr Default Description