Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 241
PCI Express Non-Transparent Bridge
3.20.2.3 PCICMD: PCI Command Register (Dev#N, PCIE NTB Sec Mode)
This register defines the PCI 3.0 compatible command register values applicable to PCI
Express space.
Register:PCICMD
Bar:PB01BASE + 500h + Offset, SB01BASE + 500h + Offset
Bus:M
Device:0
Function: 0
Offset:04h
Bit Attr Default Description
15:11 RV 00h
Reserved. (by PCI SIG)
10 RW 0
INTxDisable: Interrupt Disable
Controls the ability of the PCI-Express port to generate INTx messages.
This bit does not affect the ability of Intel
®
Xeon
®
processor C5500/C3500
series to route interrupt messages received at the PCI-Express port.
However, this bit controls the generation of legacy interrupts to the DMI
for PCI-Express errors detected internally in this port (e.g. Malformed TLP,
CRC error, completion time out etc.) or when receiving RP error messages
or interrupts due to HP/PM events generated in legacy mode within Intel
®
Xeon
®
processor C5500/C3500 series. See the INTPIN register in Section
3.20.2.18, “INTPIN: Interrupt Pin Register” on page 251 for interrupt
routing to DMI.
1: Legacy Interrupt mode is disabled
0: Legacy Interrupt mode is enabled
9RO 0
Fast Back-to-Back Enable
Not applicable to PCI Express must be hardwired to 0.
8RO 0
SERR Enable
For PCI Express/DMI ports, this field enables notifying the internal core
error logic of occurrence of an uncorrectable error (fatal or non-fatal) at
the port. The internal core error logic of IIO then decides if/how to escalate
the error further (pins/message etc.). This bit also controls the
propagation of PCI Express ERR_FATAL and ERR_NONFATAL messages
received from the port to the internal IIO core error logic.
1: Fatal and Non-fatal error generation and Fatal and Non-fatal error
message forwarding is enabled
0: Fatal and Non-fatal error generation and Fatal and Non-fatal error
message forwarding is disabled
See the PCI Express Base Specification, Revision 2.0 for details of how this
bit is used in conjunction with other control bits in the Root Control
register for forwarding errors detected on the PCI Express interface to the
system core error logic.
7RO 0
IDSEL Stepping/Wait Cycle Control
Not applicable to PCI Express must be hardwired to 0.
6RW 0
Parity Error Response
For PCI Express/DMI ports, IIO ignores this bit and always does ECC/
parity checking and signaling for data/address of transactions both to and
from IIO. This bit though affects the setting of bit 8 in the PCISTS (see bit 8
in
Section 3.19.2.4) register.
5RO 0
VGA palette snoop Enable
Not applicable to PCI Express must be hardwired to 0.
4RO 0
Memory Write and Invalidate Enable
Not applicable to PCI Express must be hardwired to 0.