Datasheet

Features Summary

Intel

Xeon

Processor C5500/C3500 Series

Datasheet, Volume 1 February 2010

24 Order Number: 323103-001

1.0 Features Summary

1.1 Introduction

This Datasheet describes DC and AC electrical specifications, signal integrity,

differential signaling specifications, pinout and signal definitions, interface functional

descriptions, and additional feature information pertinent to the implementation and

operation of the Intel

Xeon

processor C5500/C3500 series on its respective

platform.

The Intel

Xeon

processor C5500/C3500 series is the next generation of multi-core

embedded/server family of processors built on 45-nanometer process technology.

Included in this family of processors is an integrated memory controller (IMC) and

integrated I/O (IIO). The IIO provides PCI Express*, DMI, SMBus, Intel

QuickData

Technology (DMA architecture), Intel

VTd-2 for server security, etc. All of this is

integratated on a single silicon die.

Based on low-power/high-performance Intel

Core

processor, the Intel

Xeon

processor C5500/C3500 series allows for a two-chip uni-processor (UP) platform as

opposed to the traditional three-chip platforms (processor, MCH, and ICH). The two-

chip platform consists of a processor and the Platform Controller Hub (PCH). This two-

chip platform enables higher performance, lower cost, easier validation and an

improved x-y footprint.

In addition, a dual-processor (DP) configuration is supported for more performance-

demanding applications. This configuration adds an additional Intel

Xeon

processor

C5500/C3500 series. The processor and the chipset (PCH) comprise the Picket Post UP

and DP platforms illustrated respectively in Figure 1 on page 25 and Figure 2 on

page 26.

Throughout this document, the Intel

Xeon

processor C5500/C3500 series might be

referred to as the “processor”.