Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
238 Order Number: 323103-001
3.20 PCI Express Configuration Registers (NTB Secondary Side)
3.20.1 Configuration Register Map (NTB Secondary Side)
This section covers the NTB secondary side configuration space registers.
When configured as an NTB there are two sides to discuss for configuration registers.
The primary side of the NTB’s configuration space is located on Bus 0, Device 3,
Function 0 with respect to the Intel
®
Xeon
®
processor C5500/C3500 series and a
secondary side of the NTB’s configuration space is located on some enumerated bus on
another system and does not exist as configuration space on the local Intel
®
Xeon
®
processor C5500/C3500 series system anywhere.
The primary side registers are discussed in Section 3.19, “PCI Express Configuration
Registers (NTB Primary Side)”
This section discusses the secondary side registers.
Figure 62 illustrates how each PCI Express port configuration space appears to
software. Each PCI Express configuration space has three regions:
• Standard PCI Header - This region is the standard PCI-to-PCI bridge header
providing legacy OS compatibility and resource management.
• PCI Device Dependent Region - This region is also part of standard PCI
configuration space and contains the PCI capability structures and other port
specific registers. For the IIO, the supported capabilities are:
— SVID/SDID Capability
— Message Signalled Interrupts
—Power Management
— PCI Express Capability
• PCI Express Extended Configuration Space - This space is an enhancement
beyond standard PCI and only accessible with PCI Express aware software. The IIO
supports the Advanced Error Reporting Capability in this configuration space.
Figure 62. PCI Express NTB Secondary Side Type0 Configuration Space
PCI Header
0x00
PCI Device
Dependent
Extended
Configuration Space
0x40
0x100
0xFFF
MSICAPID
0x60
0x80
MSIXCAPID
CAPPTR
0x34
PXPCAPID
0x90
0xE0
PMCAP