Datasheet
PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
236 Order Number: 323103-001
3.19.4.33 LNKSTS2: PCI Express Link Status 2 Register
The PCI Express Link Status 2 register provides information on the status of the PCI
Express Link current De-emphasis level and other definition is currently reserved.
3.19.4.34 CTOCTRL: Completion Time-out Control Register
BDF 030 Offset 1E0H. This register exist in both RP and NTB modes. It is documented
in RP Section 3.4.5.35, “CTOCTRL: Completion Timeout Control Register”. See
Volume 2 of the Datasheet.
3.19.4.35 PCIE_LER_SS_CTRLSTS: PCI Express Live Error Recovery/Stop and
Scream Control and Status Register
BDF 030 Offset 1E4H. This register exist in both RP and NTB modes. It is documented
in RP Section 3.4.5.35, “PCIE_LER_SS_CTRLSTS: PCI Express Live Error Recovery/Stop
and Scream Control and Status Register”. See Volume 2 of the Datasheet.
3.19.4.36 XPCORERRSTS - XP Correctable Error Status Register
BDF 030 Offset 200H. This register exist in both RP and NTB modes. It is documented
in RP Section 3.4.5.33, “XPCORERRSTS - XP Correctable Error Status Register” . See
Volume 2 of the Datasheet.
3.19.4.37 XPCORERRMSK - XP Correctable Error Mask Register
BDF 030 Offset 204H. This register exist in both RP and NTB modes. It is documented
in RP Section 3.4.5.32, “XPCORERRMSK - XP Correctable Error Mask Register”. See
Volume 2 of the Datasheet.
3.19.4.38 XPUNCERRSTS - XP Uncorrectable Error Status Register
BDF 030 Offset 208H. This register exist in both RP and NTB modes. It is documented
in RP Section 3.4.5.24, “XPUNCERRSTS - XP Uncorrectable Error Status Register”. See
Volume 2 of the Datasheet.
3.19.4.39 XPUNCERRMSK - XP Uncorrectable Error Mask Register
BDF 030 Offset 20CH. This register exist in both RP and NTB modes. It is documented
in RP Section 3.4.5.25, “XPUNCERRMSK - XP Uncorrectable Error Mask Register” . See
Volume 2 of the Datasheet.
Register:LNKSTS2
Bus:0
Device:3
Function:0
Offset:1C2h
Bit Attr Default Description
15:01 RO 0h Reserved
00 RO 0b
Current De-emphasis Level: When the Link is operating at 5 GT/s speed,
this bit reflects the level of de-emphasis.
Encodings:
1b -3.5 dB
0b -6 dB
The value in this bit is undefined when the Link is operating at 2.5 GT/s speed.