Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 235
PCI Express Non-Transparent Bridge
3.19.4.32 LNKCON2: PCI Express Link Control Register 2
Register:LNKCON2
Bus:0
Device:3
Function: 0
Offset:1C0h
Bit Attr Default Description
15:13 RO 0 Reserved
12 RWS 0
Compliance De-emphasis – This bit sets the de-emphasis level in
Polling.Compliance state if the entry occurred due to the Enter
Compliance bit being 1b.
Encodings:
1b -3.5 dB
0b -6 dB
11 RWS 0
Compliance SOS - When set to 1b, the LTSSM is required to send SKP
Ordered Sets periodically in between the (modified) compliance
patterns.
10 RWS 0
Enter Modified Compliance - When this bit is set to 1b, the device
transmits Modified Compliance Pattern if the LTSSM enters
Polling.Compliance sub state.
9:7 RWS 0
Transmit Margin - This field controls the value of the non de-
emphasized voltage level at the Transmitter pins.
6RWO 0
Selectable De-emphasis - When the Link is operating at 5.0 GT/s
speed, this bit selects the level of de-emphasis for an Upstream
component.
Encodings:
1b -3.5 dB
0b -6 dB
When the Link is operating at 2.5 GT/s speed, the setting of this bit
has no effect.
Note: This register is not PCIE compliant. It is reserved for endpoints but
design accommodates this capability.
5RW 0
Hardware Autonomous Speed Disable: IIO does not change link speed
autonomously other than for reliability reasons.
4RWS 0
Enter Compliance: Software is permitted to force a link to enter Compliance
mode at the speed indicated in the Target Link Speed field by setting this bit to
1b in both components on a link and then initiating a hot reset on the link.
3:0 RWS
See
Description
Target Link Speed - This field sets an upper limit on link operational speed
by restricting the values advertised by the upstream component in its training
sequences.
Defined encodings are:
0001b 2.5Gb/s Target Link Speed
0010b 5Gb/s Target Link Speed
All other encodings are reserved.
If a value is written to this field that does not correspond to a speed included
in the Supported Link Speeds field, IIO will default to Gen1 speed.
This field is also used to set the target compliance mode speed when software
is using the Enter Compliance bit to force a link into compliance mode.
For PCI Express ports (Dev#1-10), this field defaults to 0001b if Gen2_OFF
fuse is ON. And when Gen2_OFF fuse is OFF this field defaults to 0010b.
For Device 0 this field defaults to 0001b.