Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
234 Order Number: 323103-001
3.19.4.31 DEVCTRL2: PCI Express Device Control 2 Register
Register:DEVCTRL2
Bus:0
Device:3
Function:0
Offset:1B8h
Bit Attr Default Description
15:6 RO 0h
Reserved
5RW 0
Alternative RID Interpretation (ARI) Enable - When set to 1b, ARI is
enabled for the NTB EP.
Note: The BIOS must leave this bit at its default value.
4RW 0
Completion Time-out Disable – When set to 1b, this bit disables the
Completion Time-out mechanism for all NP tx that IIO issues on the PCIE/DMI
link and in the case of Intel
®
QuickData Technology DMA, for all NP tx that
DMA issues upstream. When 0b, completion time-out is enabled.
Software can change this field while there is active traffic in the RP.
3:0 RW 0000b
Completion Time-out Value on NP Tx that IIO issues on PCIE/DMI – In
Devices that support Completion Time-out programmability, this field allows
system software to modify the Completion Time-out range. The following
encodings and corresponding time-out ranges are defined:
0000b = 10ms to 50ms
0001b = Reserved (IIO aliases to 0000b)
0010b = Reserved (IIO aliases to 0000b)
0101b = 16ms to 55ms
0110b = 65ms to 210ms
1001b = 260ms to 900ms
1010b = 1s to 3.5s
1101b = 4s to 13s
1110b = 17s to 64s
When OS selects 17s to 64s range, BDF 030 Offset 232H. This register exists
in both RP and NTB modes. It is documented in RP Section 3.4.5.34,
“XPGLBERRPTR - XP Global Error Pointer Register” in Volume 2 of the
Datsheet. It further controls the time-out value within that range. For all other
ranges selected by OS, the time-out value within that range is fixed in IIO
hardware.
Software can change this field while there is active traffic in the RP.