Datasheet

PCI Express Non-Transparent Bridge

Intel

Xeon

Processor C5500/C3500 Series

Datasheet, Volume 1 February 2010

232 Order Number: 323103-001

0 RW 0b System Error on Correctable Error Enable

This field controls notifying the internal core error logic of the occurrence of a

correctable error in the device.

The internal core error logic of IIO then decides if/how to escalate the error

further (pins/message

etc.). See Section 11.1, “IIO RAS Overview” (IIO

Platform Architecture Specification) for details of how/which system

notification is generated for a PCI Express correctable error.

1 = Indicates that an internal core error logic notification should be generated

if a correctable error (ERR_COR) is reported by this port.

0 = No internal core error logic notification should be generated on a

correctable error (ERR_COR) reported by this port.

Generation of system notification on a PCI Express correctable error is

orthogonal to generation of an MSI interrupt for the same error. Both a system

error and MSI can be generated on a correctable error or software can chose

one of the two. See the PCI Express Base Specification, Revision 1.1 for details

of how this bit is used in conjunction with other error control bits to generate

core logic notification of error events in a PCI Express/DMI port.

Bus:0

Device:3

Function:0

Offset:1ACh

Bit Attr Default Description