Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 231
PCI Express Non-Transparent Bridge
3.19.4.29 ROOTCON: PCI Express Root Control Register
The PCI Express Root Control register specifies parameters specific to the root complex
port.
Note: Since this PCI Express port can be configured as RP or NTB when configured as NTB
register is moved from standard location and used to unable error reporting for
upstream notification to the local host that is physically attached to the NTB.
Register:ROOTCON
Bus:0
Device:3
Function:0
Offset:1ACh
Bit Attr Default Description
15:5 Rsvd
P
0h Reserved.
4 RWL 0b CRS software visibility Enable
Note: This bit appears as RO to SW
3 RWL 0b PME Interrupt Enable
There are no PME events for NTB
Note: This bit appears as RO to SW
2 RW 0b System Error on Fatal Error Enable
This field enables notifying the internal core error logic of occurrence of an
uncorrectable fatal error at the port.
The internal core error logic of IIO then decides if/how to escalate the error
further (pins/ message etc.). See Section 11.5, “PCI Express* RAS” (IIO
Platform Architecture Specification) for details of how/which system
notification is generated for a PCI Express/DMI fatal error.
1 = Indicates that a internal core error logic notification should be generated
if a fatal error (ERR_FATAL) is reported by this port.
0 = No internal core error logic notification should be generated on a fatal
error
(ERR_FATAL) reported by this port.
Generation of system notification on a PCI Express/DMI fatal error is
orthogonal to generation of an MSI interrupt for the same error. Both a system
error and MSI can be generated on a fatal error or software can chose one of
the two.
See the PCI Express Base Specification, Revision 1.1 for details of how this bit
is used in conjunction with other error control bits to generate core logic
notification of error events in a PCI Express/DMI port.
1 RW 0b System Error on Non-Fatal Error Enable
This field enables notifying the internal core error logic of occurrence of an
uncorrectable non-fatal error at the port.
The internal core error logic of IIO then decides if/how to escalate the error
further (pins/ message etc.). See Section 11.1, “IIO RAS Overview” (IIO
Platform Architecture Specification) for details of how/which system
notification is generated for a PCI Express/DMI non-fatal error.
1 = Indicates that a internal core error logic notification should be generated
if a non-fatal error (ERR_NONFATAL) is reported by this port.
0 = No internal core error logic notification should be generated on a non-
fatal
error (ERR_NONFATAL) reported by this port.
Generation of system notification on a PCI Express/DMI non-fatal error is
orthogonal to generation of an MSI interrupt for the same error. Both a system
error and MSI can be generated on a non-fatal error or software can chose one
of the two. See the PCI Express Base Specification, Revision 1.1 for details of
how this bit is used in conjunction with other error control bits to generate
core logic notification of error events in a PCI Express/DMI port.