Datasheet
PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
230 Order Number: 323103-001
3RW1C 0h
Presence Detect Changed
This bit is set by the IIO when a Presence Detect Changed event is detected.
It is subsequently cleared by software after the field has been read and
processed.
On-board logic per slot must set the VPP signal corresponding this bit
inactive if the FF/system does not support out-of-band presence detect.
2RW1C 0h
MRL Sensor Changed
This bit is set by the IIO when an MRL Sensor Changed event is detected. It
is subsequently cleared by software after the field has been read and
processed.
On-board logic per slot must set the VPP signal corresponding this bit
inactive if the FF/system does not support MRL.
1RW1C 0h
Power Fault Detected
This bit is set by the IIO when a power fault event is detected by the power
controller. It is subsequently cleared by software after the field has been
read and processed.
On-board logic per slot must set the VPP signal corresponding this bit
inactive if the FF/system does not support power fault detection.
0RW1C 0h
Attention Button Pressed
This bit is set by the IIO when the attention button is pressed. It is
subsequently cleared by software after the field has been read and
processed.
On-board logic per slot must set the VPP signal corresponding this bit
inactive if the FF/system does not support attention button.
IIO silently discards the Attention_Button_Pressed message if received from
PCI Express link without updating this bit.
Register:SLTSTS
Bus:0
Device:3
Function:0
Offset:1AAh
Bit Attr Default Description