Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 229
PCI Express Non-Transparent Bridge
3.19.4.28 SLTSTS: PCI Express Slot Status Register
The PCI Express Slot Status register defines important status information for
operations such as Hot-plug and Power Management.
Register:SLTSTS
Bus:0
Device:3
Function:0
Offset:1AAh
Bit Attr Default Description
15:9 RsvdZ 0h Reserved.
8RW1C 0h
Data Link Layer State Changed
This bit is set (if it is not already set) when the state of the Data Link Layer
Link Active bit in the Link Status register changes.
Software must read Data Link Layer Active field to determine the link state
before initiating configuration cycles to the hot plugged device.
7RO 0h
Electromechanical Latch Status
When read this register returns the current state of the Electromechanical
Interlock (the EMILS pin) which has the defined encodings as:
0b Electromechanical Interlock Disengaged
1b Electromechanical Interlock Engaged
6RO 0h
Presence Detect State
For ports with slots (where the Slot Implemented bit of the PCI Express
Capabilities Registers is 1b), this field is the logical OR of the Presence
Detect status determined via an in-band mechanism and sideband Present
Detect pins. See the PCI Express Base Specification, Revision 2.0 for how
the inband presence detect mechanism works (certain states in the LTSSM
constitute “card present” and others don’t).
0: Card/Module/Cable slot empty or Cable Slot occupied but not powered
1: Card/module Present in slot (powered or unpowered) or cable present
and powered on other end
For ports with no slots, IIO hardwires this bit to 1b.
Note: OS could get confused when it sees an empty PCI Express RP i.e.
“no slots + no presence”, since this is now disallowed in the spec. So
BIOS must hide all unused RPs devices in IIO config space, via the
DEVHIDE register in Intel
®
QPI Configuration Register space.
5RO 0h
MRL Sensor State
This bit reports the status of an MRL sensor if it is implemented.
0: MRL Closed
1: MRL Open
4RW1C 0h
Command Completed
This bit is set by the IIO when the hot-plug command has completed and the
hot-plug controller is ready to accept a subsequent command. It is
subsequently cleared by software after the field has been read and
processed. This bit provides no guarantee that the action corresponding to
the command is complete.